1. Field of the Invention
Embodiments of the invention relates to differential amplifier circuits stably operated by low power supply voltages.
2. Related Art
A differential amplifier circuit is widely used as an element forming each of principal parts in various kinds of electronic circuits such as comparators and operational amplifiers, for example. Moreover, various kinds of low power supply voltage and low power consumption type differential amplifier circuits have been recently developed which are mounted in electronic devices in vehicles or ships for being used for detecting various kinds of information from sensors. As is shown in FIG. 4, a diagram schematically showing an example of the configuration of a related differential amplifier circuit, a differential amplifier circuit 1 of this kind is formed with a differential amplifier 2 and an inverting amplifier 3 provided. The differential amplifier 2 amplifies the differential voltage of paired input voltages and the inverting amplifier 3 carries out inverting amplification of the output of the differential amplifier 2 and externally outputs the output subjected to the inverting amplification.
The differential amplifier 2, as is shown in, for example, FIG. 5, a diagram showing an example of the configuration of the differential amplifier 2 in the differential amplifier circuit 1 shown in FIG. 4, is provided with MOS-FETs 2a and 2b as a first and second transistors, respectively, forming a differential pair and MOS-FETs 2c and 2d as a third and fourth transistors forming the loads of the MOS-FETs 2a and 2b, respectively. The differential amplifier 2 is further formed with a MOS-FET 2e as a fifth transistor provided which forms the current source of the differential pair. See Japanese Patent Application Publication No. JP-A-2007-109034).
Specifically, the MOS-FETs 2a and 2b are formed of n-channel enhancement mode MOS-FETs to the drains of which the MOS-FETs 2c and 2d are connected, respectively. Along with this, the sources of the MOS-FETs 2a and 2b are connected to each other, by which a differential pair is formed in which the MOS-FETs 2a and 2b have their gates provided as a pair of signal input terminals IN1 and IN2, respectively. Moreover, the MOS-FETs 2c and 2d forming the loads of the MOS-FETs 2a and 2b, respectively, are formed of n-channel depletion mode MOS-FETs and are provided with the sources thereof connected to their respective gates and, along with this, with each of the drains thereof connected to a power supply terminal +V on the positive side. In addition, the MOS-FET 2e is formed of an n-channel enhancement mode MOS-FET having the drain thereof connected to the sources of the MOS-FETs 2a and 2b and, along with this, having the source thereof connected to a power supply terminal −V on the negative side and being operated as a constant current source with a specified bias voltage VG applied to the gate thereof.
The bias voltage VG applied to the gate of the MOS-FET 2e is established so that a saturation current flowing between the drain and the source of the MOS-FET 2e becomes a little larger than a current flowing between the drain and the source of each of the MOS-FETs 2c and 2d, on the order of 1.5 times, for example.
The inverting amplifier 3, as is shown in FIG. 6, a diagram showing an example of the configuration of the inverting amplifier 3 in the differential amplifier circuit 1 shown in FIG. 4, for example, is formed with a MOS-FET 3b as a seventh transistor with a MOS-FET 3a as a sixth transistor provided as a load. The MOS-FET 3a forming the load is formed of an n-channel depletion mode MOS-FET and is provided with the source thereof connected to the gate thereof and, along with this, with the drain thereof connected to a power supply terminal +V on the positive side. The MOS-FET 3b is formed of an n-channel enhancement mode MOS-FET, for example, and is provided with the drain thereof having the source and the gate of the MOS-FET 3a connected thereto and, along with this, with the source connected to the power supply terminal −V on the negative side. In addition, the MOS-FET 3b carries out an inverting operation with the gate thereof receiving an output signal from the differential amplifier 2 and outputs the drain voltage thereof to the outside as an output voltage approximately equal to the power supply voltage Vdd or equal to zero level.
Here, the case will be considered in which the differential amplifier circuit 1 is used as a comparator with a reference voltage Vref is set at the signal input terminal IN2 of the differential amplifier circuit 1 and an input voltage Vin given to the signal input terminal IN1 of the differential amplifier circuit 1. When the relationship between the input voltage Vin and the reference voltage Vref is given as Vin>Vref, it is required for turning-off the MOS-FET 2b in the differential amplifier 2 shown in FIG. 5 that the drain-source voltage Vds(e) of the MOS-FET 2e and the operating threshold voltage Vth(b) of the MOS-FET 2b satisfy the condition with respect to the reference voltage Vref asVds(e)>Vref−Vth(b).  (1)
The condition that an output voltage Vout outputted from an output terminal OUT2 of the differential amplifier 2 becomes the closest to a voltage V(−) applied to the power supply terminal −V on the negative side is that the drain-source voltage Vds(c) of the MOS-FET 2c is equal to or more than the pinch-off voltage to cause the region between the drain and the source of the MOS-FET 2c to be in a pinched-off state. The pinch-off condition is shown as the relationship between the drain-source voltage of Vds(c) of the MOS-FET 2c and the operating threshold voltage Vth(c) of the MOS-FET 2c asVds(c)>−Vth(c).  (2)
Therefore, the power supply voltage Vcc of the differential amplifier circuit 1 (i.e. the differential amplifier 2) satisfying the conditions given by the expressions (1) and (2) is required to satisfy the following condition when letting a voltage applied to the power supply terminal +V on the positive side be V(+) and a voltage applied to the power supply terminal −V on the negative side be V(−):Vcc=V(+)−V(−)>Vds(e)+{−Vds(c)},that is,Vcc>Vref−Vth(b)−Vth(c).  (3)
Specifically, when the operating threshold voltage Vth(b) of the MOS-FET 2b is 1V, the operating threshold voltage Vth(c) of the MOS-FET 2c is −2V, and the reference voltage Vref is set at 1.5V, the power supply voltage Vcc required for driving the differential amplifier 2 is obtained from the expression (3) as being 2.5V or more as a necessary condition.
While, in the inverting amplifier 3, when the voltage applied to the gate of the MOS-FET 3b (the output voltage Vout of the differential amplifier 2) shown in FIG. 6 is larger than the operating threshold voltage Vth(b) of the MOS-FET 3b, it is desirable that the drain-source voltage Vds(a) of the MOS-FET 3a is that in a pinched-off state. The pinched-off condition is shown as the relationship between the drain-source voltage Vds(a) of the MOS-FET 3a and the operating threshold voltage Vth(a) of the MOS-FET 3a asVds(a)>−Vth(a).  (4)
The power supply voltage Vdd of the inverting amplifier 3 is required to satisfy the following condition when letting a voltage applied to the power supply terminal +V on the positive side be V(+) and a voltage applied to the power supply terminal −V on the negative side be V(−):Vdd=V(+)−V(−)>Vds(a),that is,Vdd>−Vth(a).  (3)
Thus, when the operating voltages Vth(c), Vth(d) and Vth(a) of the MOS-FETs 2c, 2d and 3a, respectively, are assumed to be equal to one another, the power supply voltage Vcc of the differential amplifier 2 is required to be higher than the power supply voltage Vdd required for the inverting amplifier 3 by Vref−Vth(b) or more.
In the differential amplifier 2 in the differential amplifier circuit 1, currents flowing therein are only drain-source currents of the MOS-FETs 2c and 2d each being in the order of microamperes with very small current consumption. In the inverting amplifier 3, however, a current flows also in the load (not shown) connected to the out put terminal OUT thereof. Therefore, when the power supply voltage Vdd of the inverting amplifier 3 is 3V and the value of the load thereof is 10 kΩ, for example, a current as much as 300 μA flows in the inverting amplifier 3.
Thus, for reducing the current consumption with the conditions for the power supply voltages for the differential amplifier 2 and the inverting amplifier 3 explained in the foregoing satisfied and with the condition for the output current for the inverting amplifier 3 satisfied, it becomes necessary to provide an independent power supply system for each of the differential amplifier 2 and the inverting amplifier 3. To provide two power supply systems for the differential amplifier circuit 1 of this kind, however, not only impairs the general versatility thereof but also becomes a cause of worsening the ease of operation thereof.